1. Field of the Invention
The present invention relates generally to techniques for measuring the speed of memory unit in an integrated circuit (IC), and more specifically to a built-in hardware arrangement for measuring a time interval between two consecutive outputs of the memory unit.
2. Description of the Related Art
As is known in the art, it is very important to precisely determine the speed of memory unit that is provided in an IC. A useful measure of the speed of memory unit is the time that elapses between the initiation of an operation and the completion of that operation. This is referred to as the memory access time. Another important measure is the memory cycle time, which is the minimum time delay required between the initiation of two successive memory operations.
One known technique of measuring the speed of IC memory is to successively apply memory addresses from external and detect each memory output. An IC tester is used to measure the time delay between the application of each address and the detection of the data derived from the memory. As is known, a buffer amplifier is provided between the memory and the output pins. This buffer amplifier unit inherently provides a relatively large amount of delay before the data is derived from the memory unit via the IC output pins. Thus, with the above mentioned method, it is very difficult to accurately measure the speed of memory unit.
Another approach to measuring the memory speed is to provide a memory speed measuring unit within an IC memory itself. One example of such techniques is disclosed in Japanese Laid-open Patent Application No. 4-274100. According to this conventional technique, a plurality of delay elements are incorporated in an IC memory module to determine a memory access time. However, this technique detects a memory access time at a time interval which is determined by the delay elements and accordingly, it is not expected to precisely determine the speed of memory unit.